Posts with the tag Verilog:

FPGA design for Software Engineers, part 4 - Multiplexed Seven Segment Displays

This time we’ll continue from the last design article and add in the ability to drive multiple seven segment displays.

FPGA Design for Software Engineers, Part 3 - Seven Segment Displays

Last time we took a break from Verilog and hardware design to improve our build system. This time we’re back to Verilog and for our next FPGA project we’ll create a seven segment driver circuit that will allow us to output hex characters to a single display.

A seven segment display is a set of LEDs arranged like an eight plus a decimal point like you see on cheap alarm clocks and the like.

A typical seven segment display

FPGA Design for Software Engineers, Part 1 - Verilog and State Machines

Over the last few years I’ve gotten more interested in electronics and FPGA design. I’ve also noticed that a lot of other software folks seem interested in doing the same, but often don’t know where to start. So, I think I have some interesting advice for software engineers that feel like dipping their toes into the hardware world from the point of view of a software engineer.

In this post I’ll go over FPGAs in general, the basics of the Verilog language, simulating a design and deploying it to an inexpensive TinyFPGA-BX board.