Rust vs. Zig and testz

Earlier this year I made the switch from using C++ on my hobby projects to trying out Rust. I spent about 6 months of hobby night-time programming time porting over my 2D game engine and the bulk of my 6502 CPU emulator project. There are a lot of aspects of Rust that are great, but I got tired of fighting the borrow checker left and right. I still feel like I have a hard time expressing myself in Rust.

I had heard about and looked at the Zig programming language before and really liked some of its core concepts such as comptime for doing meta-programming in a much cleaner way than I’ve seen before. This was back when it was around 0.7 and it was pretty rough around the edges in many other areas though.

I had another look towards the end of summer and found with version 0.11 it struck a chord with me and I’ve been using it ever since, getting further into a new porting exercise for my 2D game engine and 6502 CPU emulator in less than half the time it took me in Rust. I also wrote a small unit testing library for Zig called testz to improve my testing development flow.

FPGA design for Software Engineers, part 4 - Multiplexed Seven Segment Displays

This time we’ll continue from the last design article and add in the ability to drive multiple seven segment displays.

Neovim with a Little Bit of Config is Amazing

I’ve recently switched from using Visual Studio Code as my main editor of choice to using Neovim with the awesome Astronvim configuration and some of my own tweaks on top. It ends up functioning as a great development environment with code hints, debugging, file finder and at the same time uses much less memory. It even has one killer feature over VS Code.

Rust unit test layout

I’ve been succeeding in my fourth attempt at learning to use Rust. I come from mostly a C++ background, and I’ve struggled the first couple of times I’ve tried to pick up Rust, ultimately stopping the effort to work on the next shiny quarter. I started porting over my Nintendo 6502 processor emulator from C++ as a larger project to play around with. One thing I had done in the C++ one is have tons of tests for the different instructions - checking clock cycles and internal register states for the emulated CPU.

FPGA design for Software Engineers - Build System Updates, ECP5 Support

It’s been a while since the last article and I’ve recently come back to playing with my FPGA repo. Given the amount of time that has passed there were some updates needed for the Dockerfile and a couple of improvements I wanted to make.

FPGA Design for Software Engineers - Docker Builds

As I mentioned in the last blog post I recently switched my laptop over to using Linux as my main OS from Windows 10. As part of that I was going through setting up all of my build tools for various projects and I realized the FPGA build system was a bit more cumbersome than it needed to be and, utilizing docker, it could be made more developer friendly.

Switching to Kubuntu 20.10 as primary OS

About a week ago, I decided to give another go at using Linux as my primary OS. This came about after my brother mentioned he had recently done the same and was really enjoying it. I’ve used Linux as my main OS a few times before, along with MacOS a few times as well, but I always ended up back to using Windows. Recently with WSL I had less cause to need Linux directly, but a couple of things spurred me on to reconsider.

FPGA Design for Software Engineers, Part 3 - Seven Segment Displays

Last time we took a break from Verilog and hardware design to improve our build system. This time we’re back to Verilog and for our next FPGA project we’ll create a seven segment driver circuit that will allow us to output hex characters to a single display.

A seven segment display is a set of LEDs arranged like an eight plus a decimal point like you see on cheap alarm clocks and the like.

A typical seven segment display

FPGA Design for Software Engineers, Part 2 - Simulation and Build Tools

It’s been a while since the last article, but it was well received so thanks to everyone for the great feedback!

This time we’ll take a quick break from learning Verilog to set up a better simulation environment and build process using Cmake and Conan.

The next article, which is already basically written, will be back to hardware design, using seven segment displays.

FPGA Design for Software Engineers, Part 1 - Verilog and State Machines

Over the last few years I’ve gotten more interested in electronics and FPGA design. I’ve also noticed that a lot of other software folks seem interested in doing the same, but often don’t know where to start. So, I think I have some interesting advice for software engineers that feel like dipping their toes into the hardware world from the point of view of a software engineer.

In this post I’ll go over FPGAs in general, the basics of the Verilog language, simulating a design and deploying it to an inexpensive TinyFPGA-BX board.

Bitfield widths in C/C++ structures

Recently, I learned about a feature in C and C++ that I hadn’t run into before: bit widths for fields in structures. The idea is that you can specify how many bits a particular field should have allocated to it. For example, you can have a field that is only 5 bits wide and therefore only takes values in [0, 32). You could then have a field that is 3 bits wide that is placed next to the first field in memory.

Passive and Active, Consuming and Producing

I was thinking recently about the different things I choose to do in my free time and which ones bring me the most enjoyment. I tend to have too many hobby projects going on at once and every three months or so, I naturally tend to cycle around. I realized I enjoyed my time the most when I had something to show for it: a written blog post, a finished circuit on a breadboard, or some module written towards some software project.